Given an ISA with 4 instructions of 16 bits:

Instruction LW: LW rt, desp.(rs)

Code: 010s ssss tttt tddd

(s -> rs, t -> rt, d -> desp.)

Instruction SW: SW rt, desp.(rs)

Code: 001s ssss tttt tddd

(s -> rs, t -> rt, d -> desp.)

Instruction ADDI: ADDI rt, cons

Codificación: 011t tttt cccc cccc

(s -> rs, t -> rt, c -> cons)

Instruction J: J dir

Code: 101d dddd dddd dddd

(d -> dir)

Provide the code of the following instruction:

ADDI r3, 11

Give the hexadecimal (4 digit) representation with capital letters: h

Consider an instruction which copies the content of operand 2 (OP2) into operand 1 (OP1):

MV OP1, OP2

with binary code:

Consider the following addressing modes for operand 2 (OP2) :

• Immediate (unsigned decimal in binary)
• Direct to register
• Direct to memory
• Indirect register-memory
• Indirect memory-memory
• Relative to register R1

The memory and register file content is given in the tables:

give the values that are loaded into operand 1 (read from operand 2) according to the following addressing modes for operand 2:

For the

general purpose machine studied in session 3, write a code that given 2 numbers

A and B that iteratively enter in gate IN computes for the gate OUT the expression

Don't bother about the control signals, just write each instruction, e.g. mem[4]<-- IN, mem[5]<--R0, OUT<--R0+3

Write operation and comment like in the team exercise in the textbox down here

Given the instruction format design of team PEBKAC ERROR in session 4 of the classes. Give a hexadecimal code of the instruction LOAD R5, 100

Given an instruction format with two types of instructions:

Given an instruction format with two types of instructions:

Given the following processor specification

• Can handle up to 128 instuctions
• Number of general registers: 16
• Number of memory positions: 64

Give some answers on the instruction format. Give the number of bits

• for the OPCODE field

• for a field containing the direct address of a register
• for a field containing the direct address of a memory position
• for a field that indirectly addresses via a register
• required in total for relative addressing with an explicit register base and an offset represented in 2C with range [-32,31]

Code for this format the instruction:  ldr r14, [r0, #28]

where

• the first operand (r14) has direct register addressing
• the second operand ([r0, #28]) has relative addressing with explicit register base

The field order in the format is: opcode, operand1, operand2 (register), operand2 (offset).

Let the opcode of ldr consist of all bits on 0.

• Give the binary code to the instruction

• Code the instruction in hexadecimal using Capital letters and 6 digits h

Given the following 16 bits instrucion format with two types.

The memory is addressed on word level, where each word has 16 bits

. Give (in

number of bytes) the size of the memory that can be addressed by

direct addressing mode to memory. The answer should be a decimal number (e.g. 254)