Надано частину VHDL програми: signal a,b: std_logic_vector( 3 downto...
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Надано частину VHDL програми:
signal a,b: std_logic_vector(3 downto 0);
signal c: std_logic_vector(7 downto 0);
c <= a & b;
Чому дорівнюватиме С, якщо а=00
01,
b=0010?100%
0%
0%
0%
0%
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