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Read Only Memory (ROM) called CEDRIX_XT has a 3-bit input ADDRESS and a 3-bit output DATA_OUT. CEDRIX_XT has truth table as follows:
ADDRESS
|
DATA_OUT
|
001
|
001
|
010
|
010
|
011
|
100
|
for all other values
|
111
|
Write the complete code for the VHDL Test Bench required for behavioural simulation of
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