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A DMA engine saves the CPU from spending lots of its cycles copying data from memory to a device by telling the DMA engine where the data is and where its going and letting it access memory directly.

A DMA engine is a thread created by each running process automatically on modern systems that buffers I/O requests until the CPU is under-utilized and then directly copies the data from memory to the device.

A DMA engine is a special bus (connection) that connects a disk directly to memory, making data transfers faster.

Suppose a disk's bandwidth (peak performance) is 40MB/s and positioning time is 10ms. What does the chunk size need to be to achieve 80% peak performance?

The most expensive (in terms of time) phase of I/O is usually:

Acquiring and releasing locks.

Seek.

Assume a file system with 8-KB blocks and 4-byte disk addresses. If an inode has 4 direct pointers and one indirect pointer, what is the maximum size of a file it can contain?

What is the primary purpose of a Translation Lookaside Buffer (TLB)?

To cache recent virtual-to-physical address translations

To store the entire page table

To handle page faults

To allocate physical memory

For what reason would you implement a page table with three or more levels?

The virtual address space needs to be divided into three distinct segments

The page directory for a two-level page table would be too large to fit in a single page

The page table for a two-level page table would be too large to fit in a single page

To support three different page sizes simultaneously

What is the main disadvantage to flushing the TLB on a context switch?

TLBs are very large, so flushing all of the data is prohibitively expensive to perform on every context switch.

Flushing the TLB will destroy the memory of any process that is ready but not yet running.

The process about to be scheduled may require a translation used by another process.

It is a difficult task to allocate the memory required to store the TLB in physical memory, and therefore better to not reallocate with each context switch.

Each time a process is rescheduled it is likely to have a high TLB miss rate at first, and therefore slower performance.

Consider a system that has a 16KB address space and 64 byte pages and both page table entries and page directory entries are 4 bytes each. How many page directory entries are there?

2⁴

2¹⁴

2⁸

Consider the following workload :

Job A arrives at time 0s and runs for 6s

Job B arrives at time 1s and runs for 6s

Job C arrives at time 2s and runs for 3s

What is the average turnaround time (rounded to two decimal places) using the SJF scheduling policy?

Consider a standard system 64-bit address space system and assume PTEs and PDEs are each 2 bytes. What is the smallest page size we can use to avoid a page table with more than two levels (i.e., to avoid having multiple page directories)?

2⁶⁴ bytes